The present invention relates to a semiconductor memory device and, more particularly, to a technique which may be effectively applied to a semiconductor integrated circuit device having a static random-access memory (hereinafter referred to as an "SRAM").
Each of the memory cells in an SRAM generally comprises a flip-flop and two transfer MISFET's. The flip-flop is composed of a pair of inverter circuits each comprising of a high-resistance load element and a drive MISFET, the input and output terminals of these inverter circuits being cross-coupled, and the transfer MISFET's are respectively connected a pair of input and output terminals of the flip-flop. The above-described high-resistance load element is constituted by a polysilicon film which is formed integral with wiring for the power supply voltage for the purpose of reducing the memory cell area.
The polysilicon film used as the high-resistance load element has no n-type impurity (i.e., As or P) introduced therein so that the film has a relatively high resistance. On the other hand, the polysilicon film used as the power supply voltage wiring has the above-described n-type impurity introduced therein. Such technique is disclosed in U.S. Pat. No. 4,554,279 (Japanese Patent Laid-Open No. 130461/1982).